FIG. 1 schematically shows a portion of a component combining a VDMOS transistor and a logic circuit. This component includes an N-type substrate generally formed of an N-type epitaxied layer 1 formed on an N+-type substrate 2. A power transistor is formed in the right-hand portion and a logic well is formed in the left-hand portion.
The power transistor includes a set of identical cells connected to one another, such as cell 3. Each cell includes a P-type well 4, the central portion 5 of which is more heavily doped. An N-type ring 6 is formed in the upper portion of the well. The portion separating the external periphery of the N-type ring from the external periphery of the P-type well is coated with an insulated gate 8. The N-type ring 6, as well as central portion 5 of the well, are coated with a metallization 9. All gates 8 are connected to a gate terminal G and all metallizations 9 are connected to a source terminal S. The rear surface of the structure is coated with a drain metallization D. Thus, when a gate signal is applied, a current is likely to flow from terminal D to terminal S. More specifically, the current likely flows from N regions 1 and 2 to N region 6, via a channel formed under the insulated gates. This structure is generally used so that the drain is biased at a positive potential with respect to the source.
Although identical "cells" have been mentioned, the power transistor can have a digited structure. Regions 6 are then not "rings". This vocabulary will however be kept hereafter to simplify the discussion.
Logic circuits are formed in one or several wells 10. An elementary MOS transistor having drain, source, and gate terminals d, s and g has been shown in the well 10. This is only an example of a component likely to be formed in a logic well.
In some applications, a high positive overvoltage is likely to exist between the drain and the source while the MOS power transistor is blocked, or during a phase of switching to the off state. Such an overvoltage is likely to have the junction between substrate 1 and well 10 reverse breakdown and to cause the destruction of logic components formed in this well. To avoid this phenomenon, when such an overvoltage appears, it is known to momentarily restart the power transistor to have the overvoltage flow down through the power transistor. However, known solutions have several disadvantages which will be discussed hereafter.
FIG. 2 shows an example of a switched-mode power supply circuit in which an overvoltage is likely to occur on a power transistor. An input voltage V.sub.in is applied to a primary 20 of a transformer, a secondary 21 of which is connected to a capacitor 22 via a diode 23. An output voltage V.sub.out is available across capacitor 22. The second terminal of primary 20 is connected to the supply ground via an integrated component including a vertical MOS power transistor TP and a logic circuit 27. This logic circuit includes a terminal connected to the drain terminal of the power transistor, corresponding to the rear surface of the component of FIG. 1, a terminal connected to the ground and at least one input terminal 28 receiving control signals. This logic circuit 27 is especially meant for controlling the gate of the power transistor.
The operation of a switched-mode power supply is well known by those skilled in the art. It consists of periodically switching power transistor TP.
The operation upon switching of this power transistor will be described in relation with FIG. 3 which shows, as a function of time, drain voltage VD of the power transistor and current ID generally flowing through the component.
In an initial time period, between times t0 and t1, the power transistor is blocked and the voltage thereacross is equal to voltage V.sub.in. Then, the power transistor has been turned on until a time t2, when the power transistor is desired to be turned back off. Normally, the voltage across this component increases until a value V.sub.in +(V.sub.out +V.sub.F)(np/ns), where V.sub.in designates the voltage at the transformer primary, V.sub.out the voltage at the transformer secondary, V.sub.F the forward voltage drop of diode 23, and np/ns the transformation ratio of the transformer. Then, at a time t3, once the transformer is demagnetized, the voltage drops to value V.sub.in.
A problem which often arises is that the transformer has a certain parasitic inductance, associated to this transformer or to its connection wires, and that, immediately after time t2, a strong overvoltage occurs. Since the power transistor is then in an off phase, this overvoltage has a tendency to generate a current in the most fragile portion of the component, that is, through the junction between the substrate and the logic well. This overload can be destructive, as has been indicated previously.
To solve this problem, many solutions have been provided in prior art. Some of these provide the use of capacitors across the primary winding or across the power component to smoothen the overvoltage. These solutions have the disadvantage of requiring external components and of slowing down the switching, and thus of increasing energy losses in the component. Another solution is to arrange a zener diode in parallel with the power component to absorb the overload but, again, this requires the use of an external component. Eventually, this zener diode has been integrated in the monolithic structure including the power component and its logic circuit, but a zener diode of relatively large dimension must be used, and this is costly in terms of silicon surface.
The solution illustrated in FIG. 4 consists of using a zener diode Z having a protection threshold lower than the destruction threshold of power transistor TP and connected so that the zener's turning-on also turns on the power transistor. As an example, the control circuit of power transistor TP can include a current source 40 connected between the gate and the source of transistor TP, and a MOS transistor 41 in parallel to this source and likely to short-circuit the source when power transistor TP is desired to be turned off. A zener diode Z in series with a rectifying diode d is connected between the drain and the gate of the power transistor. The connection node between diodes Z and d is connected to the gate of transistor 41 via a logic circuit 42 used to turn off this transistor when the zener diode becomes conductive after an overvoltage. This control circuit will not be described in detail since it is only an example of a possibility of restart control by a zener diode Z detecting the drain voltage of a power transistor.
In practice, as shown in FIG. 5, zener diode Z is formed of a P-type region 50 formed in substrate 1. An anode metallization of this zener diode is connected to the gate of the power transistor via a diode d. Of course, this diode d will in practice be preferably integrated among the components of the logic circuit contained in well 10.
This embodiment however has a drawback illustrated in relation with FIG. 6 which shows voltage VD on the drain of MOS power transistor TP. As previously, it is assumed that transistor TP is off between times t0 and t1, and then that it is desired to turn it back off at a time t2. Then, the voltage on the drain increases until voltage V.sub.Z, then the power component is turned back on to limit the voltage thereacross to this value V.sub.Z. The phases previously described in relation with FIG. 3 are then repeated. The fast variation of the voltage across transistor TP creates a capacitive current within zener diode Z. This current tends to recharge the gate of transistor TP and thus reduces the blocking rate.
The disadvantage is that the slope of voltage VD during the blocking phase is much lower than previously, that is, the blocking duration is much longer and the losses thus increase. This is of course a disadvantage when it is desired to implement a switched-mode power supply with as fast a response time as possible. This increase of the slope is due to the existence of a stray capacitance C across zener diode Z, this stray capacitance being shown in dotted lines in FIG. 4.